RELEASED
PM73123 AAL1GATOR-8
DATASHEET
PMC-2000097
ISSUE 2
8 LINK CES/DBCES AAL1 SAR
Figure 121 RSTB Timing
16.2 SYS_CLK Timing
Table 32 SYS_CLK Timing
Symbol
Description
Min
Max
Units
fSYS
SYS_CLK Frequency (See
notes below)
25
45
MHz
dSYS
SYS_CLK Duty Cycle
40
60
Notes on SYS_CLK Timing:
1. Inputs are latched on rising edge of SYS_CLK. Outputs are driven off rising
edge of SYS_CLK.
2. If any internal TL_CLK synthesizer is used, SYS_CLK must be 38.88 MHz +/-
50 ppm.
3. If no internal TL_CLK synthesizer is used, the SYS_CLK tolerance can be
relaxed to +/- 200 ppm.
4. If it is desired that the internally synthesized TL_CLK is locked to a network
clock, then SYS_CLK needs to be locked to that network clock.
5. To maintain sufficient bandwidth on all lines, SYS_CLK must be at least 38.88
MHz. For each line that is not used on the most loaded A1SP, the minimum
frequency can be decreased by 4.5 MHz, if the internal clock synthesizers are
not used.
6. The SYS_CLK minimum frequency is due to the internal DLL.
PMC-SIERRA, INC. PROPRIETARY AND CONFIDENTIAL
337
PMC [ PMC-SIERRA, INC ]
