RELEASED
PM73123 AAL1GATOR-8
DATASHEET
PMC-2000097
ISSUE 2
8 LINK CES/DBCES AAL1 SAR
5. Data is sampled internally one SYS_CLK cycle after CSB and WRB are
detected low.
6. RDB must be high during writes.
16.5 External Clock Generation Control Interface
Table 36 External Clock Generation Control Interface
Symbol
Description
Min Max Units
f
SYS_CLK Frequency (See notes
below)
25
45
MHz
SCLK
D
SCLK
SYS_CLK Duty Cycle
40
60
%
tS
tH
tP
Input Set-up time to SYS_CLK
Input Hold time to SYS_CLK
SYS_CLK High to Output Valid
4
1
1
ns
ns
ns
12
Figure 126 External Clock Generation Control Interface Timing
SYSCLK
tS
tH
tP
CGC_SER_D
CGC_VALID
CGC_LINE
CGC_DOUT
SRTS_STBH
ADAP_STBH
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PMC [ PMC-SIERRA, INC ]
