RELEASED
PM73123 AAL1GATOR-8
DATASHEET
PMC-2000097
ISSUE 2
8 LINK CES/DBCES AAL1 SAR
16.4 MICROPROCESSOR INTERFACE TIMING CHARACTERISTICS
Table 34 Microprocessor Interface Read Access
Symbol Parameter
Min Max
Units
tSAR
tHAR
tSALR
tHALR
tVL
Address to Valid Read Set-up Time
10
5
ns
ns
ns
ns
ns
ns
ns
Address to Valid Read Hold Time
Address to Latch Set-up Time
Address to Latch Hold Time
Valid Latch Pulse Width
Latch to Read Set-up
10
10
5
tSLR
tHLR
0
Latch to Read Hold
5
tPACKL Valid Read to Valid ACKB Propagation
Delay
3
400* SYS
CLK
cycles
tZRD
tZACKH Valid Read Negated to ACK Tri-state
tSRD Data to Valid ACKB Setup time
Valid Read Negated to Output Tri-state
20
20
ns
ns
ns
5
* Microprocessor may momentarily experience excessive delays when
accessing the external SSRAM, but will average 10-15 SYSCLK cycles.
Microprocessor accesses to internal registers will not experience these
excessive delays.
PMC-SIERRA, INC. PROPRIETARY AND CONFIDENTIAL
339
PMC [ PMC-SIERRA, INC ]
