RELEASED
PM73123 AAL1GATOR-8
DATASHEET
PMC-2000097
ISSUE 2
8 LINK CES/DBCES AAL1 SAR
16.6 RAM Interface
Table 37 RAM Interface
Symbol
Description
Min
25
Max
45
Units
MHz
%
F
SYS_CLK, Frequency
SYS_CLK Duty Cycle
SCLK
D
SCLK
40
60
tS
tH
tP
tZ
Input Set-up time to SYS_CLK
Input Hold time to SYS_CLK
SYS_CLK High to Output Valid
4
ns
ns
ns
ns
1
1.5
1.5
12
12
SYS_CLK High to Output High-
Impedance
tZB
SYS_CLK High to Output Driven
1.5
12
ns
Figure 127 RAM Interface Timing
SYSCLK
tH
tP
tS
RAM_D
RAM_PAR
RAM_A
RAM_D
RAM_PAR
tP
RAM_OEB
RAM_WEB
RAM_CSB
RAM_ADSC
tZ / tZB
RAM_D
RAM_PAR
PMC-SIERRA, INC. PROPRIETARY AND CONFIDENTIAL
344
PMC [ PMC-SIERRA, INC ]
