RELEASED
PM73123 AAL1GATOR-8
DATASHEET
PMC-2000097
ISSUE 2
8 LINK CES/DBCES AAL1 SAR
13.4 External Clock Generation Control I/F (CGC)
Status information is played out on the External Clock Control (CGC) Interface
which includes the external output signals: CGC_DOUT(3:0), CGC_LINE(3:0),
SRTS_STBH, and ADAP_STBH.
Information is played out for all chip modes (Direct and H-MVIP).
The interface clocking operates according to the following pseudocode:
• If a channel pair is being serviced, start a state machine to play out the
channel status, as shown in Table 27 asserting ADAP_STBH as each state is
played out.
• Else, if an SRTS difference value is ready, it is played out with SRTS_STBH
asserted and ADAP_STBH deasserted.
• Else if a cell is received and a valid averaged relative buffer depth can be
computed, start a state machine to play out the averaged relative buffer depth
and queue number, as shown in Table 28, asserting ADAP_STBH as each
state is played out.
• Once playout of a certain data type has begun if will not be interrupted.
13.4.1 SRTS Data Output
In SRTS mode the CGC block puts out a 4 bit value which represents the
difference between the local SRTS value and the received SRTS value. Figure
105 below shows a typical CGC output in SRTS mode.
Figure 105 SRTS Data
SYSCLK
ECC_DOUT[3:0]
DATA
LINE
ECC_LINE[4:0]
SRTS_STBH
ADAP_STBH
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PMC [ PMC-SIERRA, INC ]
