RELEASED
PM73123 AAL1GATOR-8
DATASHEET
PMC-2000097
ISSUE 2
8 LINK CES/DBCES AAL1 SAR
Each entry within the Transmit Idle State FIFO indicates the channel responsible
for the interrupt and certain status information depending on the selected
DBCES mode. See the section on DBCES in the TX A1SP section which
discusses the different DBCES words and the structure of the entries in the Idle
State FIFO.
9.4.2 Add Queue FIFO
In order to add a queue the processor has to write the ADDQ_FIFO. The
ADDQ_FIFO consists of 64 16-bit entries and is accessed using a single
address. The format of the ADDQ_FIFO word is shown in Figure 69. The first
byte specifies the number of the queue to be added. The next six bits represent
an offset that is used to spread the scheduling of cells across multiple frames.
This helps to avoid the problem of clumping, which refers to contention with other
cells scheduled during the same frame (see section 9.2.1.2.1 on Transmit CDV).
The upper bit indicates whether or not the ADDQ_FIFO is empty. This bit can be
polled after adding queues to find out when they all have been added. The
Empty bit indicates Empty status when it is set. The amount of time it takes to
empty the FIFO is dependent on how full it is, whether TALP is processing cells
and whether there is back pressure on the UTOPIA bus. ADDQ_FIFO entries
can only be processed when TALP is idle. If the TALP_FIFO fills and prevents
TALP from processing cells, this will prevent ADDQ_FIFO entries from being
processed.
Note that the Offset and Queue Number fields are write only and cannot be read.
The Empty field is read only and cannot be written.
Figure 69 ADDQ_FIFO Word Structure
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Empty
Unused
Offset
Queue Number
It is necessary to understand the basics of the frame-based scheduling
performed by the chip to best utilize the Offset field in the ADDQ_FIFO. Read
Section 9.2.1.2 and pay particular attention to how the Transmit Calendar works
and to Section 9.2.1.2.1 and the information on clumping. The purpose of the
offset field in the ADDQ_FIFO is to reduce the amount of clumping.
In frame mode (SDF-FR), the first cell of a queue can be scheduled relative to a
reference value. When REF_VAL_ENABLE=0 in the LIN_STR_MODE memory
mapped register, the reference value is always frame 0. When
REF_VAL_ENABLE =1, the reference value is based upon the configuration
PMC-SIERRA, INC. PROPRIETARY AND CONFIDENTIAL
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