RELEASED
PM73123 AAL1GATOR-8
DATASHEET
PMC-2000097
ISSUE 2
8 LINK CES/DBCES AAL1 SAR
For SDF-MF DBCES queues, OFFSET must be set equal to
FRAMES_PER_CELL.
In summary, when REF_VAL_EN is set, the generated CDV for the following two
configurations will be minimized, more closely approaching the ideal minimum
CDV for each case (REF_VAL_EN provides no added value for other
configurations.):
• All 24(32) Queues SDF-FR, Single-DS0-with-no-pointer, full cells, Ideal
minimum CDV = 0 us. Clumping is guaranteed not to occur.
• All 24(32) Queues SDF-MF, Single-DS0, full cells, Ideal minimum CDV = 125
us. Clumping is minimized.
IMPORTANT NOTE:
If a multiframe resync occurs on a line and REF_VAL_ENABLE is set, the
relationship between different queues on that line will change. If this occurs,
clumping may occur in the existing connections and in any future connections
that are added. In H-MVIP mode, multiframe resyncs will never occur. In low
speed mode, if REF_VAL_ENABLE is set it is recommended that
MF_SYNC_MODE in LS_Ln_CFG_REG is disabled, as this will prevent
multiframe resyncs.
9.5 RAM Interface Block (RAMI)
The RAMI is the central arbiter for all memory accesses. It provides a priority
mechanism that incorporates fairness to satisfy all real-time requirements of the
various blocks. All blocks requesting a data transfer with the common memory
supply the address, control signals, and the data, if the requested data transfer is
a write, to the RAMI. When the RAMI actually grants the transfer, it provides a
grant signal to the requesting block, indicating that the transfer has been
performed. The memory is arbitrated on a cycle-by-cycle basis. No device is
granted the bus for an indefinite time.
The AAL1gator-8 has a separate SSRAM and processor interface. One 128K x
16 SSRAM is needed. Either a pipelined synchronous SRAM with a single cycle
deselect or a pipelined ZBT or ZBT-compatible synchronous SRAM can be used.
For most applications the pipelined single-cycle deselect SSRAM is sufficient,
but if additional performance is needed, such as in cross connect applications
which need to use partial cells to lower delay, the ZBT SSRAM is recommended.
PMC-SIERRA, INC. PROPRIETARY AND CONFIDENTIAL
161
PMC [ PMC-SIERRA, INC ]
