RELEASED
PM73123 AAL1GATOR-8
DATASHEET
PMC-2000097
ISSUE 2
8 LINK CES/DBCES AAL1 SAR
six possible sources of an interrupt for the A1SP_INTR_REG: A1SP Receive
Status FIFO not empty, A1SP Transmit Idle State FIFO not empty, A1SP Receive
Status FIFO overflow, Transmit Idle State FIFO overflow, OAM interrupt, and
Frame Advance FIFO overflow. The OAM interrupt indicates that the Receive
OAM Queue is not empty. In other words, this interrupt can be thought of as an
active low Receive OAM Queue Empty signal. The A1SP Receive Status FIFO
overflow, A1SP Transmit Idle State FIFO overflow, and Frame Advance FIFO
overflow interrupts simply indicate that the FIFOs have overflowed. The A1SP
Receive Status FIFO not empty interrupt indicates the A1SP Receive Status
FIFO is not empty and the A1SP Transmit Idle State FIFO not empty interrupts
do the same. The next two sections discuss how these FIFOs operate.
Since some of the conditions are transitory, the A1SP_INTR_REG captures if the
condition has occurred since the last time the register was read. The
A1SP_STAT_REG reflects the current status.
9.4.1.3.1 A1SP Receive Status FIFO
The Receive Status FIFO (RCV_STAT_FIFO) consists of 64 entries and is
contained internal to the chip. The FIFO is accessed using a single address.
When the FIFO transitions from empty to not empty, the INTR_FIFO_EMPB bit
in both the A1SP_INTR_REG and the A1SP_STAT_REG will go active. When
there are no longer any entries in the FIFO, the INTR_FIFO_EMPB bit in the
A1SP_STAT_REG will go inactive.
Each entry within the Interrupt FIFO indicates the queue responsible for the
interrupt and one of four possible causes: DBCES bitmask change, exiting
underrun, entering underrun, and receive queue error. The first cause reports a
change in the bit mask for DBCES. The second two causes simply report a
change in the underrun status, while the third cause indicates an error has
occurred on the receive side. To find out the specific cause of the error, the
processor should access the R_ERROR_STKY register for the queue
responsible for the interrupt. An error entry will only occur for the latter case if
this is the first unmasked sticky bit error to occur for this queue since the last
time the sticky bit memory register was cleared.
9.4.1.3.2 A1SP Transmit Idle State FIFO
The Transmit Idle State FIFO consists of 64 entries and is contained internal to
the chip. The FIFO is accessed using a single address port. When the FIFO
transitions from empty to not empty, the TX_IDLE_FIFO_EMPB bit in both the
A1SP_INTR_REG and the A1SP_STAT_REG will go active. When there are no
longer any entries in the FIFO, the Transmit Idle State FIFO not empty interrupt
bit in the A1SP_STAT_REG will go inactive.
PMC-SIERRA, INC. PROPRIETARY AND CONFIDENTIAL
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PMC [ PMC-SIERRA, INC ]
