RELEASED
PM73123 AAL1GATOR-8
DATASHEET
PMC-2000097
ISSUE 2
8 LINK CES/DBCES AAL1 SAR
Figure 67 below shows the format of the Normal Mode Registers block in more
detail.
Figure 67 Normal Mode Registers Memory Map
80000
Command Reigsters
800FF
80100
RAM Interface Registers
8011F
80120
UTOPIA Interface Registers
801FF
80200
Line Interface Reigsters
80FFF
81000
Interrupt and Status Registers
812FF
Idle Channel Configuration and
82000
Status Registers
Registers
82FFF
84000
DLL Control and Status Registers
Registers
84FFF
9.4.1 Interrupt Driven Error/Status Reporting
The interrupt logic has several layers and can be sourced from any of three
blocks. The three blocks are the UTOPIA block, the RAM interface block, and
the A1SP block. The top layer of the interrupt logic, the Master Interrupt
Register, indicates from which block the interrupt came from. Once the block is
determined the processor can access the appropriate block to determine the
interrupt cause.
Figure 68 shows the registers in the interrupt tree. The microprocessor traverses
the tree based on the value of individuals bits within each register.
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