RELEASED
PM73123 AAL1GATOR-8
DATASHEET
PMC-2000097
ISSUE 2
8 LINK CES/DBCES AAL1 SAR
Figure 68 Interrupt Hierarchy
MSTR_INTR_REG
Top Level
2nd Level
A1SP_INTR_REG
Utopia
INTR
RAM INTR
A1SP_TIDLE_FIFO
RCV_STAT_FIFO
R_ERROR_STKY
3rd Level
A1SP Interrupts
A1SPn Interrupts
4th Level
9.4.1.1 UTOPIA Interrupts
The UTOPIA block sources five interrupts directly to the Master Interrupt
Register. The five interrupts are Transmit UTOPIA FIFO full, Loopback FIFO
full, UTOPIA parity error, runt cell error, and UTOPIA transfer error. The first
interrupt indicates that the Transmit UTOPIA four cell FIFO has filled. The
second interrupt indicates that the UTOPIA loopback FIFO has filled. The third
interrupt indicates there was a parity error on the data received on the UTOPIA
interface. The fourth interrupt indicates cell less than 53 bytes was detected.
The fifth interrupt indicates the receive UTOPIA interface was requested to send
a cell when it did not have one available.
9.4.1.2 RAM Interface Interrupts
The RAM interface block sources a parity error interrupt directly to the Master
Interrupt Register.
9.4.1.3 A1SP Interrupts
The A1SP block sources an interrupt to the Master Interrupt Register. The A1SP
interrupt register indicates the source of the interrupt within the A1SP block.
Since many indications provided by the A1SP interrupt structure are per channel
or per queue, there are 2 FIFOs provided for per channel indications. There are
PMC-SIERRA, INC. PROPRIETARY AND CONFIDENTIAL
157
PMC [ PMC-SIERRA, INC ]
