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PM73121-RI 参数 Datasheet PDF下载

PM73121-RI图片预览
型号: PM73121-RI
PDF下载: 下载PDF文件 查看货源
内容描述: AAL1分段重组处理器 [AAL1 Segmentation And Reassembly Processor]
分类和应用: ATM集成电路SONET集成电路SDH集成电路电信集成电路电信电路异步传输模式
文件页数/大小: 223 页 / 2148 K
品牌: PMC [ PMC-SIERRA, INC ]
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PM73121AAL1gator II  
Data Sheet  
PMC-Sierra, Inc.  
PMC-980620  
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AAL1 SAR Processor  
The TUTOPIA responds to the /TATM_FULL signal. If the signal is not asserted, and the TUTO-  
PIA has data to send, it will do so by asserting /TATM_EN. If /TATM_FULL is asserted, then the  
data flow will be paused in exactly two clock cycles, until the /TATM_FULL signal allows the  
cell to be completed. See the timing diagram in Figure 25 on page 42.  
TATM_CLK(i)  
/TATM_FULL(i)  
/TATM_EN(o)  
TATM_SOC(o)  
TATM_DATA(o)  
53  
01  
02  
03  
04  
05  
06  
07  
Figure 25. Transmit UTOPIA Timing (ATM Mode)  
In PHY mode, the TUTOPIA block sources RPHY_DATA(7:0), RPHY_SOC, and RPHY_  
CLAV, while receiving /RPHY_EN. The SOC indication is generated coincident with the first  
byte of each cell that is transmitted on RPHY_DATA. In PHY mode, the RATM_DATA and  
RATM_SOC signals are driven only when valid data is being sent; otherwise they are tristated.  
/RPHY_ADDR is an input and is used only in MPHY mode.  
The cell available (RPHY_CLAV) signal indicates when the device has a complete cell to send.  
In SPHY mode, RPHY_CLAV is always driven. If in MPHY mode, the output enable for this sig-  
nal is the /RPHY_ADDR input delayed by one cycle. In MPHY mode, /RPHY_ADDR is tied to  
one of the address signals so RPHY_CLAV is driven only when polled.  
The UTOPIA standard defines a 5-bit address. Since the AAL1gator II has only a single active  
low address bit, multiple AAL1gator II devices can be connected in parallel to the same MPHY  
interface by connecting each one to a separate address bit. In this manner, five AAL1gator IIs can  
be connected to an MPHY interface using the following addresses: “0Fh”, “17h”, “1Bh”, “1Dh”,  
and “1Eh” with no additional logic. If other addresses are needed or additional devices are to be  
connected to the same interface, additional logic may be required.  
If a cell is being read in SPHY mode, or is being read from a channel that is being polled in  
MPHY mode, the value of RPHY_CLAV will be 1 until the cell has been read out of the FIFO  
and there are no more cells to send. In PHY mode, the TUTOPIA block is dependent on the ATM  
device to read the data by asserting the /RPHY_EN input. In SPHY mode, data is placed on  
RPHY_DATA any cycle following one in which /RPHY_EN was asserted. In MPHY mode, in  
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