PM73121ꢀAAL1gator II
Data Sheet
PMC-Sierra, Inc.
PMC-980620
,VVXHꢀꢁ
AAL1 SAR Processor
order to output data, the TUTOPIA block also has to be selected, which is done when /RPHY_
ADDR is low on the falling edge of /RPHY_EN. See Figure 26 on page 43 and Figure 27 on
page 43 for the TUTOPIA transfer timing diagrams.
RPHY_CLK(i)
RPHY_ADDR(i)*
RPHY_CLAV(o)***
RPHY_CLAV(o)**
RPHY_SOC(o)
RPHY_DATA(o)
D1
D2
D3
/RPHY_EN(i)
* Used only in MPHY mode
** For MPHY mode
*** For SPHY mode
Figure 26. TUTOPIA Start-of-Transfer Timing (PHY Mode)
RPHY_CLK(i)
RPHY_ADDR(i)*
RPHY_CLAV(o)**
RPHY_CLAV(o)***
RPHY_SOC(o)
RPHY_DATA(o)
/RPHY_EN(i)
D48
D49
D50
D51
D52
D53
* Used only in MPHY mode
** For MPHY mode
*** For SPHY mode
Figure 27. TUTOPIA End-of-Transfer Timing (PHY Mode)
The AAL1gator II can tolerate temporary deassertions of /TATM_FULL(/RPHY_EN), but it is
assumed that enough UTOPIA bandwidth is present to accept the cells that the AAL1gator II can
produce in a timely manner. The AAL1gator II can tolerate a deassertion of /TATM_
FULL(/RPHY_EN) for up to 128 line interface frames, but this would cause excessive CDV. The
TALP circuit writes cells one byte at a time into the FIFO. The SOC is also placed into the FIFO.
ꢃꢂ
PMC [ PMC-SIERRA, INC ]
