PM73121ꢀAAL1gator II
Data Sheet
PMC-Sierra, Inc.
PMC-980620
,VVXHꢀꢁ
AAL1 SAR Processor
Clocking for the read side is derived from the system clock. If the FIFO is full, the cell building
process stalls until space becomes available. If the FIFO remains full, additional queues will not
be able to be added. This will be indicated to the processor by the CSD_ATTN bit not being
cleared after setting that bit.
The TUTOPIA circuit controls when a cell is transmitted from the FIFO. Since the UTOPIA can
transmit cells at higher speeds than the TALP, and since it is expected to see applications in a
shared UTOPIA environment, cell transmission from the TUTOPIA commences only when there
is a full cell worth of data available to transmit. The cell is then transmitted to the interface at the
UTOPIA TATM_CLK rate, in accordance with the /TATM_FULL (/RPHY_EN) input. The max-
imum supported clock rate is 33 MHz.
3.5 Receive UTOPIA Interface Block (RUTOPIA)
The RUTOPIA block receives cells from the UTOPIA interface and sends them to the RALP
interface. Depending on the value of the PHY_ENABLE input pin, the UTOPIA interface acts
either as an ATM side (controls the read enable signal) or as a PHY side (controls the cell avail-
able signal). As a PHY-side device, the RUTOPIA block can also act as an SPHY device or as an
MPHY device (refer to the UTOPIA Level 2 specification in Appendix B, “References”, on
page 203) depending on the value of SPHY_EN in COMP_LIN_REG. The SPHY_EN bit
defaults to MPHY mode, so if the device is in an MPHY environment, there will not be any con-
tention while the chip is in software reset.
In ATM mode, the RUTOPIA block receives RATM_DATA(7:0), RATM_SOC, and /RATM_
EMPTY while driving /RATM_EN. At reset the RUTOPIA block activates /RATM_EN to pre-
vent excessive queueing in the system. After the end of reset, if the /RATM_EMPTY input signal
is not asserted, the RUTOPIA block waits for an RATM_SOC signal from the PHY layer. Once
the RATM_SOC signal arrives, the cell is accepted as soon as possible. A small intermediate
FIFO allows the interface to accept data at the maximum rate. If the FIFO fills, the /RATM_EN
signal will not be asserted again until the device is ready to accept an entire cell. The /RATM_EN
signal depends only on the cell space and is independent of the state of the /RATM_EMPTY sig-
nal. See Figure 28 for the RUTOPIA timing diagram.
RATM_CLK(i)
/RATM_EMPTY(i)
RATM_DATA(i)
3
5
7
1
2
4
6
RATM_SOC(i)
/RATM_EN(o)
Figure 28. Receive UTOPIA Timing (ATM Mode)
ꢃꢃ
PMC [ PMC-SIERRA, INC ]
