PM73121ꢀAAL1gator II
Data Sheet
PMC-Sierra, Inc.
PMC-980620
,VVXHꢀꢁ
AAL1 SAR Processor
The RUTOPIA block waits for an SOC. When an RATM_SOC signal arrives, a counter is started,
and 53 bytes are received. If a new RATM_SOC occurs within a cell, the counter reinitializes.
This means that the corrupted cell will be dropped and the good cell will be received. The RUTO-
PIA block stores the ATM cell in the receive FIFO. If the receive FIFO becomes full, it stops
receiving ATM cells from the PHY layer. The /RATM_EMPTY signal can also turn on or off any
time, even if the /RATM_EN signal is on. As a result, an incoming byte is valid only when
/RATM_EN is active and /RATM_EMPTY is inactive. The bytes are written to the FIFO with
RATM_CLK. RATM_CLK is an input to the AAL1gator II. The maximum supported clock rate
is 33 MHz.
In PHY mode, the RUTOPIA block receives TPHY_DATA(7:0), TPHY_SOC, and /TPHY_EN
while driving TPHY_CLAV. The cell available (TPHY_CLAV) signal indicates when the device
is ready to receive a complete cell. In SPHY mode, TPHY_CLAV is always driven. In MPHY
mode, the output enable for this signal is the /TPHY_ADDR input delayed by one cycle. In
MPHY mode, /TPHY_ADDR is tied to one of the address signals so that TPHY_CLAV is driven
only when polled.
The UTOPIA standard defines a 5-bit address. Since the AAL1gator II has only a single active
low address bit, multiple AAL1gator II devices can be connected in parallel to the same MPHY
interface by connecting each one to a separate address bit. In this manner, five AAL1gator IIs can
be connected to an MPHY interface using the following addresses: “0Fh”, “17h”, “1Bh”, “1Dh”,
and “1Eh” with no additional logic. If other addresses are needed or additional devices are to be
connected to the same interface, additional logic may be required.
At reset, the RUTOPIA block tristates TPHY_CLAV. After the end of reset, the RUTOPIA block
waits for /TPHY_EN to be asserted, and in SPHY mode, will accept data as long as /TPHY_EN is
asserted. In MPHY mode, /TPHY_ADDR must be low on the falling edge of /TPHY_EN in order
for the RUTOPIA block to accept the data. When SOC is detected, a counter is started and
53 bytes are received. If a new TPHY_SOC occurs within a cell, the counter reinitializes. This
means that the corrupted cell will be dropped and the good cell will be received. A small interme-
diate FIFO allows the interface to accept data at the maximum rate. If the FIFO fills, the TPHY_
ꢃꢄ
PMC [ PMC-SIERRA, INC ]
