PM73121ꢀAAL1gator II
Data Sheet
PMC-Sierra, Inc.
PMC-980620
,VVXHꢀꢁ
AAL1 SAR Processor
Tp - Tch
- Rs -10 ≥ 0.5 ns
max
A 2.5% duty cycle CMOS clock source at 38.88 MHz has a Tch
13.5 ns at 2.5 V.
of 12.2 ns and a Tch
of
max
min
A rise/fall time of 0.5 ns (from 20-80%) results in a gain of 0.33 ns at 1.5 V and would change
Tch to 12.53 ns.
min
A rise/fall time of 2 ns (from 20-80%) results in a gain of 1.33 ns at 1.5 V and would change
Tch to 14.83 ns.
max
Replacing Tch and Tch
in the equations above gives:
min
max
Rs ≥ 8.5 + 4.3 -12.53 ≥ 0.27 ns
Rs ≤ 25.7 - 14.83 - 10 - 0.5 ≤ 0.37 ns
Referring to Table 24 on page 175, selecting a 33 Ω resistor would meet both of these
requirements.
In summary, a possible solution when using an SRAM with 8 ns setup is to use a 2.5% duty cycle
CMOS clock (with a minimum rise/fall time of 0.5 ns and a maximum rise/fall time of 2 ns) and a
33 Ω series resistor. To improve margin, either the duty cycle needs to be tightened or the
maximum rise time needs to be reduced, which would allow a larger resistor.
8.6.5 Layout
The delay information provided assumes a 15 pF load on the /MEM_WE signals that have one
load and a 30 pf load on the MEM_DATA outputs that have two loads. The trace capacitance is
approximately 2 pF per inch and the input pin capacitance is about 7 pF. Therefore, the SRAM
trace lengths should be approximately four inches long.
Also, the series resistor should be placed as close as possible to the source pin.
ꢀꢆꢈ
PMC [ PMC-SIERRA, INC ]
