PM73121ꢀAAL1gator II
Data Sheet
PMC-Sierra, Inc.
PMC-980620
,VVXHꢀꢁ
AAL1 SAR Processor
8.9 Interfacing with the ATM Cell Multiplexer (WAC-185-B-X)
Figure 95 shows the interface for connecting eight AAL1gator IIs (as PHY layer devices) to the
ATM Cell Multiplexer (WAC-185-B-X), an ATM layer device. Configure the AAL1gator IIs in
Multi-PHY UTOPIA mode by connecting the PHY_ENABLE input pin to V , and setting the
CC
SPHY_EN bit to “0” in the COMP_LIN_REG memory word (refer to section 7.4.2 “COMP_
LIN_REG” on page 125). Configure the WAC-185-B-X in Multi-PHY UTOPIA mode by setting
the ATM_MPHY_EN bit to “1” in the GEN_5 microprocessor port. In this mode, the
WAC-185-B-X will drive the eight addresses x00, x01, x02, x03, x04, x05, x06, and x07, and the
null address x1F onto the RATM_ADDR/TATM_ADDR busses. The decoding logic shown in
Figure 95 should decode each of these addresses to an active low enable signal for each of the
AAL1gator IIs.
If only four, or fewer, AAL1gator IIs are to be connected to the WAC-185-B-X, the external
decode logic can be eliminated by implementing a single-PHY UTOPIA bus instead of a
Multi-PHY UTOPIA bus. In this case, configure the AAL1gator IIs in single-PHY UTOPIA
mode by connecting the PHY_ENABLE input pin to V and setting the SPHY_EN bit to “1” in
CC
the COMP_LIN_REG memory word. Configure the WAC-185-B-X in single-PHY UTOPIA
mode by setting the ATM_MPHY_EN bit to “0” and the ATM_CELL_EN bit to “1” in the GEN_
5 microprocessor port. (The ATM_CELL_EN is set because the AAL1gator II implements
cell-level handshaking due to its cell-based internal FIFOs.) In this mode the WAC-185-B-X does
ꢀꢇꢂ
PMC [ PMC-SIERRA, INC ]
