PM73121ꢀAAL1gator II
Data Sheet
PMC-Sierra, Inc.
PMC-980620
,VVXHꢀꢁ
AAL1 SAR Processor
To determine Tch and Tch , the minimum and maximum duty cycle must be defined. Also if
min
max
a CMOS driver is being used, the minimum and maximum rise and fall times of the driver must be
defined.
Since high-speed SRAMS use TTL input thresholds, all output timing parameters are measured at
1.5 V. The SYS_CLK input, like all the AAL1gator II inputs, uses TTL input levels. Due to tight
timing requirements on the minimum pulse width required for SYS_CLK, a CMOS driver can be
used to generate SYS_CLK to improve the pulse width. The rise/fall time of the signal will cause
the high pulse width measured at 1.5 V to be larger then the pulse width measured at 2.5 V.
The following sections provide four case examples:
•
•
•
•
Using an SRAM with 7 ns write data setup and a TTL clock.
Using an SRAM with 7 ns write data setup and a CMOS clock.
Using an SRAM with 8 ns write data setup and a TTL clock.
Using an SRAM with 8 ns write data setup and a CMOS clock.
8.6.1 SRAM with 7 ns Write Data Setup and a TTL Clock
Referring back to the setup and hold equations:
SRAM write setup = Tch - 4.3 + Rs
min
SRAM write data hold = Tp - Tch
- Rs -10
max
Assuming we want to have a 0.5 ns margin on both setup and hold time, the requirements to meet
are:
Tch - 4.3 + Rs ≥ 7.5 ns
min
Tp - Tch
- Rs -10 ≥ 0.5 ns
max
A 5% duty cycle TTL clock source at 38.88 MHz has a Tch
at 1.5 V.
of 11.6 ns and a Tch
of 14.1 ns
max
min
Replacing Tch and Tch
in the equations above gives:
min
max
Rs ≥ 7.5 + 4.3 -11.6 ≥ 0.2 ns
Rs ≤ 25.7 - 14.1 - 10 - 0.5 ≤ 1.1 ns
Referring to Table 24 on page 175, selecting a 50 Ω resistor would meet both of these
requirements.
In summary, one possible solution when using an SRAM with 7 ns setup is to use a 5% duty cycle
TTL clock source and a 50 Ω series resistor. To increase the margin, the tolerance on the clock
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PMC [ PMC-SIERRA, INC ]
