PM73121ꢀAAL1gator II
Data Sheet
PMC-Sierra, Inc.
PMC-980620
,VVXHꢀꢁ
AAL1 SAR Processor
could be tightened, or a CMOS clock driver could be used. The rise/fall time of the clock should
be less than 1.5 ns.
8.6.2 SRAM with 7 ns Write Data Setup and a CMOS Clock
When using a CMOS clock, the rise and fall time of the clock needs to be taken into account to
determine what the pulse width will be at a TTL level. The benefit of using a CMOS clock is that
the pulse width will be wider at the TTL level then it will be at the CMOS level. Rise/fall times
for CMOS outputs are usually given from the 20% to the 80% level or across a 3 V range.
Dividing this number by 3 gives the approximate delay between the 1.5 V level and the 2.5 V
level. Since the delay occurs at both rising and falling edges, this value is doubled to give the
increase in setup time. The hold time is usually the critical factor with a CMOS clock driver.
For instance, if the rise/fall time is 3 ns, there will be a 1 ns delay from a transition at 1.5 V to the
transition at 2.5 V and, a 2 ns increase in setup time.
This time we will have 1 ns margin on setup and 0.5 ns margin on hold. The requirements to meet
are:
Tch
- 4.3 + Rs ≥ 8.0 ns
min
Tp - Tch
- Rs -10 ≥ 0.5 ns
max
A 2.5% duty cycle CMOS clock source at 38.88 MHz has a Tch
13.5 ns at 2.5 V.
of 12.2 ns and a Tch
of
max
min
A rise/fall time of 0.5 ns (from 20-80%) results in a gain of 0.33 ns at 1.5 V and would change
Tch to 12.53 ns.
min
A rise/fall time of 2 ns (from 20-80%) results in a gain of 1.33 ns at 1.5 V and would change
Tch to 14.83 ns.
max
Replacing Tch and Tch
in the equations above gives:
min
max
Rs ≥ 8.0 + 4.3 -12.53 ≥ - 0.23 ns
Rs ≤ 25.7 - 14.83 - 10 - 0.5 ≤ 0.37 ns
Referring to Table 24 on page 175 shows that selecting a 33 Ω resistor would meet both
requirements. Note that the negative resistance value in the first equation indicates additional
margin. In this situation, the hold time is more critical and is dependent on the clock duty cycle.
Selecting a 5% clock would create a hold time problem unless either the required margin was
reduced or the maximum rise time was reduced.
In summary, one possible solution when using an SRAM with 7 ns setup is to use a 2.5% duty
cycle CMOS clock (with a minimum rise/fall time of 0.5 ns and a maximum rise/fall time of 2 ns)
and a 33 Ω series resistor.
ꢀꢆꢆ
PMC [ PMC-SIERRA, INC ]
