PM73121ꢀAAL1gator II
Data Sheet
PMC-Sierra, Inc.
PMC-980620
,VVXHꢀꢁ
AAL1 SAR Processor
The following section details how to ensure the SRAM interface will work over all commercial
environmental conditions. Examples are also provided for a few different scenarios. The generic
equations are provided so other scenarios can be evaluated.
Due to its tight requirements, the write data setup and write data hold are the most critical
parameters for SRAM selection. Both of these parameters are derived from the high pulse width
of the SYS_CLK input.
The setup and hold times of the SRAM are based on:
•
•
The high time of SYS_CLK
The series termination resistor value for /MEM_WE
Adding a series resistor will increase the rise/fall time due to an increase in the RC constant.
Based on the slew rate output of the driver, the value of the resistor, and a 15 pF load, the delay at
1.5 V will be increased by the amount shown in Table 24.
Table 24. Delay Values for Different Resistors
Resistor (Ω)
Delay (ns)
33
50
0.3
0.4
0.6
0.7
75
100
Using a resistor value greater than 100 Ω is not recommended, since this will cause rise/fall times
that are too slow and will not match the board impedance close enough, which can cause
reflections.
The high pulse width of SYS_CLK, plus the delay through the resistor must ensure the rising edge
of /MEM_WE is slow enough to provide sufficient setup time, but fast enough to provide enough
hold time.
The generic equations for determining the SRAM setup and hold requirements are:
SRAM write setup = Tchmin - 4.3 + Rs
SRAM write data hold = Tp - Tchmax - Rs -10
where: Tch is the high pulse width of SYS_CLK at 1.5 V,
Tp is the clock period, and
Rs is the delay through the resistor.
ꢀꢆꢄ
PMC [ PMC-SIERRA, INC ]
