PM73121ꢀAAL1gator II
Data Sheet
PMC-Sierra, Inc.
PMC-980620
,VVXHꢀꢁ
AAL1 SAR Processor
8.7 UDF-HS Mode SRTS-Based Clock Recovery Application for DS3
While the AAL1gator II has built-in SRTS clock recovery for T1/E1 rates, external circuitry is
required for DS3/E3 rates in UDF-HS mode. SRTS-based clock recovery can be accomplished
with the circuitry shown in Figure 92. The circuit generates a clock at the 44.736 MHz DS3
frequency.
Network-
Derived
77.76 MHz
VCC
N_CLK
Ref In
D0-D7
8
AAL1gator II
(PM73121)
SRTS
EPLD
DAC
(AD7801)*
SRTS_STRB
SRTS_DOUT
4
VOUT
TL_CLK(0)
VCO
(EC3125)*
To LIU
*NOTE: Manufacturer’s data sheets are subject to change.
Please confirm specifications before using this part.
Figure 92. SRTS-Based Clock Recovery Circuit
This circuit functions as follows. The AAL1gator II asserts SRTS_STRB indicating a new SRTS
nibble is available on SRTS_DOUT. In UDF-HS mode, the SRTS_STRB and SRTS_DOUT
signals are driven from the rising edge of N_CLK, thus SRTS_STRB should be used to clock the
SRTS_DOUT nibble in D-type flip flops. Once latched, a lookup table (refer to Table 25) is used
to convert the SRTS_DOUT nibble into an 8-bit code to drive an Analog Devices’ AD7801 8-bit
®
Digital-to-Analog Converter (DAC). The DAC output voltage then controls the ECLIPTEK
EC3125 Voltage Controlled Oscillator (VCO), which has a 44.736 MHz center frequency. The
resulting DS3 clock rate is then fed to the AAL1gator II TL_CLK(0) input and the LIU. The N_
CLK must be network derived, but the SYS_CLK does not need to be network derived.
Table 25. Memory Interface System Clock Operating Conditions
SRTS_DOUT
(Binary)
8-Bit DAC Code
(Hex)
0111
0110
0101
E7
CD
C0
ꢀꢇꢉ
PMC [ PMC-SIERRA, INC ]
