PM73121ꢀAAL1gator II
Data Sheet
PMC-Sierra, Inc.
PMC-980620
,VVXHꢀꢁ
AAL1 SAR Processor
38.88 MHz
Clock
Clock
Generation
Logic
Smoother
AAL1gator II
(PM73121)
SRTS
TL_CLK
LTX305A or
T7690
Clock Generation Logic:
TL_CLK_SRC
(1.544 MHz)
DIV_25
T1 Frequency Generation
38.88 MHz
or
DIV_26
DIV_25 (158 + SRTS) Times
DIV_26 35 Times
DIV (193 + SRTS)
TL_CLK_SRC = 38.88 × (193 + SRTS) ÷ (26 × 35 + 25 × (158 + SRTS)) = 1.544 if SRTS = 0
OR
TL_CLK_SRC
(2.048 MHz)
DIV_19
or
E1 Frequency Generation
38.88 MHz
DIV_18
DIV_19 (63 - SRTS) Times
DIV_18 One Time
DIV (64 - SRTS)
TL_CLK_SRC = 38.88 × (64 - SRTS) ÷ (18 + 19 × (63 - SRTS)) = 2.048 if SRTS = 0
Figure 90. SRTS-Based Clock Recovery Circuitry
ꢀꢆꢂ
PMC [ PMC-SIERRA, INC ]
