PM73121ꢀAAL1gator II
Data Sheet
PMC-Sierra, Inc.
PMC-980620
,VVXHꢀꢁ
AAL1 SAR Processor
8.6 Board Requirements for the SRAM Interface
The AAL1gator II can use industry-standard asynchronous SRAMs for its external memory. The
AAL1gator II provides control signals that control all data accesses to the SRAM. Figure 91 is an
example of how the SRAM should be incorporated into the AAL1gator II system design.
Table 26 on page 195 lists the recommended worst-case parameters for each component. Parts
must meet these requirements to run this interface at full speed.
/MEM_WE(0)
/MEM_WE(1)
/MEM_CS
/WE(0)
/WE(1)
/CS
(2) 128K × 8
SRAMs
/OE
A(0:16)
/MEM_OE
D(0:15)
16
MEM_DATA(0:15)
MEM_ADDR(0:16)
17
AAL1gator II
(PM73121)
/SP_DATA_EN
SP_DATA_DIR
SP_DATA_CLK
/SP_ADD_EN
16
SYS_CLK
Vcc
A(0:15)
Y(0:16)
G
Octal Bus
Transceivers and
Registers
SAB
CBA
SBA
G
Octal Buffers with
Tristate Outputs
(FCT244)
DIR
CAB
(FCT646)
A(0:16)
B(0:15)
Gnd
PROC_ADD (17)
PROC_DATA (0:15)
16
PROC_ADD (0:16)
17
Microprocessor
NOTES: Series terminating resistors are 33 Ω to 100 Ω. See this application note for requirements for /MEM_WE resistors.
*Manufacturer’s data sheets are subject to change. Please confirm specifications before using this part.
Figure 91. Suggested AAL1gator II Memory Interface
SRAMs must be 12 ns or faster and must have a write data setup of 7 ns or faster to operate
at the maximum system clock rate.
ꢀꢆꢃ
PMC [ PMC-SIERRA, INC ]
