PM73121ꢀAAL1gator II
Data Sheet
PMC-Sierra, Inc.
PMC-980620
,VVXHꢀꢁ
AAL1 SAR Processor
8.4 External FIFO Application
Figure 89 shows how to connect the AAL1gator II to two 9-bit Integrated Device Technology
SyncFIFOs™. On the RATM interface, a D-type flip-flop is required on the /RATM_EMPTY
signal since the SyncFIFO /EF signal does not conform to UTOPIA timing. On the TATM
interface, the SyncFIFO must be able to accept four more data bytes after it asserts the /TATM_
FULL signal. This is accomplished by using the SyncFIFO /PAF flag and its full-7 bytes default
offset.
9
Q(8:0)
8
9
D(8:0)
TATM_DATA(7:0)
TATM_SOC
RCLK
/REN1
/EF
/TATM_FULL
/PAF
External
Transmit
FIFO
/WEN1
/TATM_EN
TATM_CLK
WCLK
(IDT SyncFIFO*)
AAL1gator II
(PM73121)
TATM_CLK_Source
9
8
8
Q(8:0)
/EF
RATM_DATA(7:0)
D(8:0)
WCLK
/WEN1
RATM_SOC
/RATM_EMPTY
D
Q
External
Receive
FIFO
CLK
/RATM_EN
RATM_CLK
/REN1
/OE
(IDT SyncFIFO*)
RCLK
/PAF
*NOTE: Manufacturer’s data sheets are subject to change.
RATM_CLK_Source
Please confirm specifications before using this part.
Figure 89. Typical External FIFO Application
ꢀꢆꢀ
PMC [ PMC-SIERRA, INC ]
