PM73121ꢀAAL1gator II
Data Sheet
PMC-Sierra, Inc.
PMC-980620
,VVXHꢀꢁ
AAL1 SAR Processor
Symbol
Parameter
Signals
Min
Max
Unit
Tq
Clock-to-output delay
SP_DATA_CLK,/MEM_OE
(deactivate)
2
15
ns
Tq
Clock-to-output delay
/MEM_CS
2
2
18
25
ns
ns
Tqmoe
Clock-to-output delay for activation MEM_OE (activate)
of /MEM_OE
Tasu17
Taed
Address setup to SYS_CLK
Address enable delay
ADDR17
2
5
ns
ns
ns
ns
/SP_ADD_EN
20
Tasu
Address setup to SP_DATA_CLK* MEM_ADDR, SP_DATA_CLK
Data enable delay from /PROC_CS /SP_DATA_EN, /PROC_CS,
and /PROC_RD
26
2**
Tded
15**
15
/PROC_RD
Tcea
/PROC_CS deassertion to /PROC_ /PROC_ACK
ACK deassertion
2
ns
Tdsu
Tdh
Data setup to SP_DATA_CLK*
Data hold from SP_DATA_CLK*
MEM_DATA
11
3
ns
ns
ns
MEM_DATA, SP_DATA_CLK
SP_DATA_CLK, /SP_ADD_EN
Tcaen
SP_DATA_CLK high to
/SP_ADD_EN high
0
Tah
MEM_ADDR hold time from SP_
DATA_CLK*
MEM_ADD, SP_DATA_CLK
MEM_ADDR
1
ns
ns
Tzsu
Z state setup-to-clock
3**
* These parameters are dependent on external components and assume that the requirements from Table 26 on page 195 are
met.
** These parameters are typical only.
NOTE: Taa is dependent on the HOLDOFF signal. If HOLDOFF is not asserted when the
access begins, Taa will be a maximum of six SYS_CLK periods. If the access occurs
immediately after another access, then Taa will be 24 to 30 SYS_CLK periods. Refer
to section 6.5.3 “Microprocessor Holdoff Timing” on page 116 for a description of
the HOLDOFF activity.
6.5.2.3 Microprocessor Write Command Register Timing
Figure 73 on page 112 shows the write command register timing. Writing to the internal com-
mand register is not honored if higher priority internal functions request the memory, or if the
holdoff from a previous microprocessor transfer has not expired.
/PROC_CS and /PROC_WR are double sampled (1 and 2) at the rising edge of SYS_CLK, and at
(3) ADDR17 is sampled to distinguish between a command register write and a RAM write.
As long as HOLDOFF is not high, /SP_ADD_EN, /SP_DATA_EN, and SP_DATA_DIR are acti-
vated at the next clock cycle (3), allowing the microprocessor address and data to pass through the
address and data buffer to the AAL1gator II. The /SP_ADD_EN and the /SP_DATA_EN signals
are delayed to minimize bus conflicts when the microprocessor access follows an
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PMC [ PMC-SIERRA, INC ]
