PM73121ꢀAAL1gator II
Data Sheet
PMC-Sierra, Inc.
PMC-980620
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AAL1 SAR Processor
AAL1gator II-initiated access. Since all address bits, except ADDR17, are ignored for command
register write operations (unless PROC_TEST_ACCESS is set (refer to “(Reserved)” on page
165)), the timing of the lower 16 address bits is not critical for this operation and is not shown.
Internally, a delayed version of SYS_CLK is used to latch the data. Since this internal clock is not
visible on the outside, no setup or hold times are given. As long as the output enable and output
disable delay of the external data buffer meet the parameters in the following table, the setup and
hold time of the internal clock will be met.
At the following clock cycle (4), /PROC_ACK is activated and /SP_DATA_EN and /SP_ADD_
EN are deactivated. The relative skew of these signals guarantees sufficient hold time. To elimi-
nate bus contention, a recovery cycle is inserted between the microprocessor access and any sub-
sequent access. /PROC_ACK is held active until /PROC_CS is deactivated.
Cycles (1) and (2) are grouped together in Figure 73 for the sake of convenience. These are nor-
mally two separate clock cycles.
NOTE: The timing characteristics (indicated by asterisks in the table following Figure 73)
are based on external component requirements.
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PMC [ PMC-SIERRA, INC ]
