PM73121ꢀAAL1gator II
Data Sheet
PMC-Sierra, Inc.
PMC-980620
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AAL1 SAR Processor
At the following clock cycle (7), /PROC_ACK is activated and MEM_DATA is deactivated. A
recovery cycle is inserted between the microprocessor access and any subsequent access to elimi-
nate bus contention. /PROC_ACK is held active until /PROC_CS is deactivated. /SP_DATA_EN
is held active until /PROC_CS or /PROC_RD is deactivated to ensure the microprocessor reads
the data.
Cycles (1) and (2) are grouped together in Figure 74 for the sake of convenience. These are nor-
mally two separate clock cycles.
NOTE: The timing characteristics (indicated by asterisks in the table following Figure 74)
are based on external component requirements.
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PMC [ PMC-SIERRA, INC ]
