PM73121ꢀAAL1gator II
Data Sheet
PMC-Sierra, Inc.
PMC-980620
,VVXHꢀꢁ
AAL1 SAR Processor
Symbol
Parameter
Signals
Min
Max
Unit
Taa
(Refer to
Acknowledge assertion after /PROC_ /PROC_ACK
CS or /PROC_WR; whichever occurs
5
29
SYS_CLK
periods
NOTE below) last
Tasu17
Tcea
Address setup to SYS_CLK
ADDR17
2
2
ns
ns
/PROC_CS deassertion to /PROC_
ACK deassertion
/PROC_ACK, /PROC_CS
15
Tded
Tq
Data enable delay from SYS_CLK
Clock-to-output delay
/SP_DATA_EN, SYS_CLK
SP_DATA_DIR
7
2
2
25
15
18
ns
ns
ns
Tq
Clock-to-output delay
/PROC_ACK
NOTE: Taa is dependent on the HOLDOFF signal. If HOLDOFF is not asserted when the
access begins, Taa will be a maximum of four SYS_CLK periods. If the access
occurs immediately after another access, then Taa will be 23 to 29 SYS_CLK peri-
ods. Refer to section 6.5.3 “Microprocessor Holdoff Timing” on page 116 for a
description of the HOLDOFF activity.
6.5.2.4 Microprocessor Read Command Register Timing
Figure 74 on page 115 shows the read command register timing. Four SYS_CLK cycles are
required to read the internal command register. However, the read operation is not honored if
higher priority internal functions request the memory, or the holdoff from a previous micropro-
cessor transfer has not expired.
The /PROC_CS and /PROC_RD signals are double sampled (1 and 2) at the rising edge of SYS_
CLK, and at (3) ADDR17 is sampled to distinguish between a command register read and a RAM
read. For microprocessor read operations, /SP_DATA_EN goes active when both /PROC_CS and
/PROC_RD are active, allowing data to pass through the data buffer to the microprocessor.
As long as HOLDOFF is not high, /SP_ADD_EN is activated at the next clock cycle (3) allowing
the microprocessor address to pass through the address buffer to the AAL1gator II and SP_
DATA_CLK is also driven low. /SP_ADD_EN is delayed to minimize bus conflicts when the
microprocessor access follows an AAL1gator II-initiated access. Since all address bits, except for
ADDR17 are ignored for command register read operations (unless PROC_TEST_ACCESS is
set), the timing of the lower 16 address bits is not critical for this operation and is not shown.
At the following clock cycle (4), /SP_ADD_EN is deactivated but /SP_DATA_EN remains
active. At clock cycle (5) the AAL1gator II begins driving valid data that is latched into the data
latch in cycle (6) when SP_DATA_CLK is driven high.
ꢀꢀꢂ
PMC [ PMC-SIERRA, INC ]
