PM6341 E1XC
DATA SHEET
PMC-910419
ISSUE 8
E1 FRAMER/TRANSCEIVER
Register 25H: FRMR Maintenance/Alarm Status Interrupt Indication
Bit
Type
Function
Default
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
R
R
R
R
R
R
R
R
RRAI
RRMAI
AISDI
X
X
X
X
X
X
X
X
T16AISDI
REDI
AISI
FEBEI
CRCEI
A logic 1 in any bit position of this register indicates which maintenance or alarm
status generated an interrupt by changing state.
RRAI, RRMAI, AISDI, T16AISDI, REDI, and AISI:
RRAI, RRMAI, AISDI, T16AISDI, REDI, and AISI indicate when the
corresponding FRMR Maintenance/Alarm Status register bit has changed
state from logic 0 to logic 1 or vice-versa.
FEBEI:
The FEBEI bit becomes a logic one when a logic zero is received in the Si
bits of frames 13 or 15.
CRCEI:
The CRCEI bit becomes a logic one when a calculated CRC differs from the
received CRC remainder.
The bits in this register are set by a single error event.
The interrupt indications within this register work independently from the interrupt
enable bits, allowing the microprocessor to poll the register to determine the
state of the framer.The contents of this register are cleared to logic 0 after the
register is read; the interrupt is also cleared if it was generated by any of the
Maintenance/Alarm Status events.
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE
129
PMC [ PMC-SIERRA, INC ]
