PM6341 E1XC
DATA SHEET
PMC-910419
ISSUE 8
E1 FRAMER/TRANSCEIVER
Register 19H: DJAT Block Reference Clock Divisor (N1) Control
Bit
Type
Function
Default
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
N1[7]
N1[6]
N1[5]
N1[4]
N1[3]
N1[2]
N1[1]
N1[0]
0
0
1
0
1
1
1
1
This register defines an 8-bit binary number, N1, which is one less than the
magnitude of the divisor used to scale down the DJAT PLL reference clock input.
The REF divisor magnitude, (N1+1), is the ratio between the frequency of REF
input and the frequency applied to the phase discriminator input.
Writing to this register will reset the PLL and, if the SYNC bit in the DJAT
Configuration register is high, will also reset the FIFO.
Upon reset of the E1XC, the default value of N1 is set to decimal 47 (2FH).
Consult the Operations section for clarification of divisor selection criteria.
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE
115
PMC [ PMC-SIERRA, INC ]
