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PM6341-QI 参数 Datasheet PDF下载

PM6341-QI图片预览
型号: PM6341-QI
PDF下载: 下载PDF文件 查看货源
内容描述: E1成帧器/收发器 [E1 FRAMER/TRANSCEIVER]
分类和应用: PC
文件页数/大小: 272 页 / 902 K
品牌: PMC [ PMC-SIERRA, INC ]
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PM6341 E1XC  
DATA SHEET  
PMC-910419  
ISSUE 8  
E1 FRAMER/TRANSCEIVER  
Register 06H: E1XCTransmit Framing Options  
Bit  
Type  
Function  
Default  
Bit 7  
Bit 6  
Bit 5  
Bit 4  
Bit 3  
Bit 2  
Bit 1  
Bit 0  
R/W  
PATHCRC  
Unused  
0
X
X
1
0
0
0
0
Unused  
R/W  
R/W  
R/W  
R/W  
R/W  
TXSA4EN  
TXSA5EN  
TXSA6EN  
TXSA7EN  
TXSA8EN  
PATHCRC:  
The PATHCRC bit allows upstream block errors to be preserved in the  
transmit CRC bits. If PATHCRC is a logic 1, the CRC-4 bits are modified to  
reflect any bit values in BTPCM which have changed prior to transmission.  
When PATHCRC is set to logic 0, the TRAN block is allowed to generate a  
new CRC-4 value which overwrites the incoming CRC-4 word. For the  
PATHCRC bit to be effective, the BTXMFP bit of the Transmit Backplane  
Options register must be a logic 1; otherwise, the identification of the  
incoming CRC-4 bits would be impossible. The PATHCRC bit only takes effect  
if the GENCRC bit of the TRAN Configuration register (44H) is a logic 1 and  
either the INDIS or FDIS bit in the same register are set to logic1.  
TXSA4EN, TXSA5EN, TXSA6EN, TXSA7EN and TXSA8EN:  
The TXSAxEN bits control the insertion of a data link into the Time Slot 0  
National Use bits (Sa4 through Sa8).  
These bits only have effect if the TRAN block Configuration DLEN bit is logic  
0 or if the TRAN block Configuration SIGEN bit is logic 1. The TXSAxEN bits  
take priority over the INDIS and FDIS bits of the TRAN block Configuration  
register. The data link bits are still inserted if either INDIS or FDIS is logic 1.  
If the TXDMASIG bit is a logic 1, the data link bits are sourced by the internal  
HDLC transmitter; otherwise, the bits are sourced from the TDLSIG pin. If the  
TXSA4EN bit is logic 1, the TDLSIG value is written into bit 4 of Time Slot 0 of  
non-frame alignment signal frames. If the TXSA8EN bit is logic 1, the  
TDLSIG value is written into bit 8 of Time Slot 0 of non-frame alignment signal  
frames. The other enable bits operate in an analogous fashion. A clock pulse  
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE  
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