PM6341 E1XC
DATA SHEET
PMC-910419
ISSUE 8
E1 FRAMER/TRANSCEIVER
is generated on TDLCLK for each enable that is logic 1. Any combination of
enable bits is allowed, resulting in a data rate between 4 kbit/s and 20 kbit/s.
Clearing all enables disables insertion. Any National Use bits which are not
included in the data link are sourced from either BTPCM or the TRAN block
International/National Control register.
Upon reset of the E1XC, all bits are logic 0 except TXSA4EN. By default, a 4
kbit/s data link is inserted into Sa4 from the TDLSIG input.
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE
83
PMC [ PMC-SIERRA, INC ]
