PMC-Sierra, Inc.
PRELIMINARY
PM5381 S/UNI-2488
DATASHEET
PMC-2000489
ISSUE 1
SATURN USER NETWORK INTERFACE FOR 2488 MBIT/S
J0Z0INCEN:
The J0 and Z0 increment enable (J0Z0INCEN) bit controls the insertion of an incremental
pattern in the section trace and Z0 growth bytes. When J0ZOINCEN is set to logic 1, the
corresponding STS-1/STM-0 path # is inserted in the J0 and Z0 bytes according to the priority
of Table 4. When J0Z0INCEN is set to logic 0, no incremental pattern is inserted.
For normal operation, the J0Z0INCEN bits in the TRMP Aux1 Configuration register, the
TRMP Aux2 Configuration register and the TRMP Aux3 Configuration register must be set to
the same value as the J0Z0INCEN bit.
TRACEEN:
The section trace enable (TRACEEN) bit controls the insertion of section trace in the data
stream. When TRACEEN is set to logic 1, the section trace from the Section TTTP block is
inserted in the J0 byte of STS-1/STM-0 #1 according to the priority of Table 4. When
TRACEEN is set to logic 0, the section trace from the J0[7:0] input port is not inserted.
TSLDEN:
The TSLD enable (TSLDEN) bit controls the insertion of section or line DCC in the data
stream. When TSLDEN is set to logic 1, the S/UNI-2488 inserts all ones or all zeros as
selected using the TSLD_VAL bit in the S/UNI-2488 Diagnostic register into the D1-D3 bytes
or D4-D12 bytes of STS-1/STM-0 #1 according to the priority of Table 4. When TSLDEN is
set to logic 0, the section or line DCC is not inserted.
TLDEN:
The TLD enable (TLDEN) bit controls the insertion of line DCC in the data stream. When
TLDEN is set to logic 1, the S/UNI-2488 inserts all ones or all zeros as selected using the
TLD_VAL bit in the S/UNI-2488 Diagnostic register into in the D4-D12 bytes of STS-1/STM-0
#1 according to the priority of Table 4. When TLDEN is set to logic 0, an all ones pattern is
not inserted.
APSEN:
The APS enable (APSEN) bit controls the insertion of automatic protection switching in the
data stream. When APSEN is set to logic 1, the APS bytes from the RRMP are inserted in
the K1/K2 bytes of STS-1/STM-0 #1 according to the priority of Table 4. When APSEN is set
to logic 0, the APS bytes from the RRMP are not inserted.
LREIEN:
The line REI enable (LREIEN) bit controls the insertion of line remote error indication in the
data stream. When LREIEN is set to logic 1, the line REI from the RRMP is inserted in the
M1 byte of STS-1/STM-0 #3 according to the priority of Table 4. When LREIEN is set to logic
0, the line REI from the RRMP is not inserted.
Proprietary and Confidentail to PMC-Sierra Inc., and for its Customer’s Internal Use
151
PMC [ PMC-SIERRA, INC ]
