PMC-Sierra, Inc.
PRELIMINARY
PM5381 S/UNI-2488
DATASHEET
PMC-2000489
ISSUE 1
SATURN USER NETWORK INTERFACE FOR 2488 MBIT/S
FIFO_CLOCK:
The FIFO Clock source selection bit is used to select the source of the FIFO output. If
FIFO_CLOCK is set to logic 1 the clock for CRU output clock is used as the reference. If
FIFO_CLOCK is set to logic 0 than the FIFO clock is obtained from the CSU.
INV_DATA:
The Serial Data Inversion INV_DATA controls the polarity of the received data. When
INV_DATA is set to ‘1’ the polarity of the RXD+/- input pins invert. When INV_DATA is set to
‘0’ the RXD+/- inputs operate normally.
LATCH_ERR_CNT:
The Latch Error Count bit loads the PRBS byte error count value. When a logic 1 is written to
this bit the PRBS byte error count register is loaded into the LATCH_ERR_CNT[7:0] register
and the PRBS byte error count is reset to zero. This bit is write only and is cleared
immediately after the write is complete.
PRBS_ERR_CNT[7:0]:
The ERR_CNT[7:0] register, is the number of errors in the PRBS bytes detected during the
monitoring. Errors are accumulated only when the monitor is in the synchronized state. Even
if there is multiple errors within one PRBS byte, only one error is counted. The transfer of the
error counter to this holding register is trigger by writing to the LATCH_ERR_CNT bit or by
pulsing high the LCLK signal. This PRBS_ERR_CNT[7:0] is cleared after it is read. The
actual PRBS error counter is cleared immediately after a logic 1 is written to the
LATCH_ERR_CNT bit. The error counter will not wrap around after reaching FFh, it will
saturate to this value.
Proprietary and Confidentail to PMC-Sierra Inc., and for its Customer’s Internal Use
128
PMC [ PMC-SIERRA, INC ]
