PMC-Sierra, Inc.
PRELIMINARY
PM5381 S/UNI-2488
DATASHEET
PMC-2000489
ISSUE 1
SATURN USER NETWORK INTERFACE FOR 2488 MBIT/S
Register 0013H: Rx2488 Analog PRBS Control
Bit
Type
R
R
R
R
R
R
R
R
Function
Default
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
PRBS_ERR_CNT[7]
PRBS_ERR_CNT[6]
PRBS_ERR_CNT[5]
PRBS_ERR_CNT[4]
PRBS_ERR_CNT[3]
PRBS_ERR_CNT[2]
PRBS_ERR_CNT[1]
PRBS_ERR_CNT[0]
LATCH_ERR_CNT
UNUSED
INV_DATA
FIFO_CLOCK
SYNC_STAT
PRBS_FPATT
PRBS_ENABLE
RESYNC
0
0
0
0
0
0
0
0
X
X
0
0
0
0
0
0
W
R/W
R/W
R
R/W
R/W
R/W
The CRU Clock Training Configuration register is provided at RCS_2488 read/write address 3.
RESYNC:
Forces the monitor to re-initialize the PRBS sequence. When set high, the monitor’s state
machine will be forced in the Out-Of-Sync state and automatically tries to resynchronize to
the incoming stream. This bit is cleared once the monitor enters the In-Sync state.
PRBS_ENABLE:
This bit enables the PRBS monitor of the RCS_2488. When low, the PRBS monitor is
disabled. When high the PRBS monitor is enabled and will check the incoming data stream
for errors.
PRBS_FPATT:
This bit determines whether the RCS_2488 is monitoring a PRBS data stream or a fixed
pattern. When low, the data stream contains PRBS bytes, and when high the fixed pattern
written into the PATTERN[15:0] Register is monitored.
SYNC_STAT:
The Monitor Synchronization Status bit reflects the state of the monitor’s state machine.
When SYNC_STAT is set low, the monitor has lost synchronization. When SYNC_STAT is
high, the monitor is in synchronization.
Proprietary and Confidentail to PMC-Sierra Inc., and for its Customer’s Internal Use
127
PMC [ PMC-SIERRA, INC ]
