PMC-Sierra, Inc.
PRELIMINARY
PM5381 S/UNI-2488
DATASHEET
PMC-2000489
ISSUE 1
SATURN USER NETWORK INTERFACE FOR 2488 MBIT/S
RCLK4EN:
The receive clock enable (RCLK4EN) bit controls the gating of the RCLK4 output clock.
When RCLK4EN is set to logic 1, the RCLK4 output clock operates normally. When
RCLK4EN is set to logic 0, the RCLK4 output clock is held low.
DISFRM:
The disable framing (DISFRM) bit disables the framing algorithm and resets the bit alignment
on the RD[15:0] input bus to none. When DISFRM is set to logic 1, the framing algorithm is
disable and the bit alignment is reset to none. When DISFRM is set to logic 0, the framing
algorithm is enable and the bit alignment is done when out of frame is declared.
DISFRM1:
The disable framing (DISFRM1) bit disables the framing algorithm and resets the bit
alignment on the RD1[7:0] input bus to none. When DISFRM1 is set to logic 1, the framing
algorithm is disable and the bit alignment is reset to none. When DISFRM1 is set to logic 0,
the framing algorithm is enable and the bit alignment is done when out of frame is declared.
DISFRM2:
The disable framing (DISFRM2) bit disables the framing algorithm and resets the bit
alignment on the RD2[7:0] input bus to none. When DISFRM2 is set to logic 1, the framing
algorithm is disable and the bit alignment is reset to none. When DISFRM2 is set to logic 0,
the framing algorithm is enable and the bit alignment is done when out of frame is declared.
DISFRM3:
The disable framing (DISFRM3) bit disables the framing algorithm and resets the bit
alignment on the RD3[7:0] input bus to none. When DISFRM3 is set to logic 1, the framing
algorithm is disable and the bit alignment is reset to none. When DISFRM3 is set to logic 0,
the framing algorithm is enable and the bit alignment is done when out of frame is declared.
DISFRM4:
The disable framing (DISFRM4) bit disables the framing algorithm and resets the bit
alignment on the RD4[7:0] input bus to none. When DISFRM4 is set to logic 1, the framing
algorithm is disable and the bit alignment is reset to none. When DISFRM4 is set to logic 0,
the framing algorithm is enable and the bit alignment is done when out of frame is declared.
ROTATEEN:
The TSI rotate enable (ROTATEEN) bit controls the TSI rotation matrix. When ROTATEEN is
set to logic 1, the TSI rotation matrix is active and the bytes on the RD[15:0] output bus are re
ordered. When ROTATEEN is set to logic 0, the TSI rotation matrix is inactive.
Proprietary and Confidentail to PMC-Sierra Inc., and for its Customer’s Internal Use
131
PMC [ PMC-SIERRA, INC ]
