PMC-Sierra, Inc.
PRELIMINARY
PM5381 S/UNI-2488
DATASHEET
PMC-2000489
ISSUE 1
SATURN USER NETWORK INTERFACE FOR 2488 MBIT/S
Register 0030H: SRLI Clock Configuration
Bit
Type
Function
Default
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
R/W
ROTATEEN
Unused
1
Unused
Unused
Unused
Unused
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
DISFRM4
DISFRM3
DISFRM2
DISFRM1
DISFRM
RCLK4EN
RCLK3EN
RCLK2EN
RCLK1EN
Unused
0
0
0
0
0
0
0
0
0
Bit 8
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
The Clock Configuration Register is provided at SRLI r/w address 0030H.
RCLK1EN:
The receive clock enable (RCLK1EN) bit controls the gating of the RCLK1 output clock.
When RCLK1EN is set to logic 1, the RCLK1 output clock operates normally. When
RCLK1EN is set to logic 0, the RCLK1 output clock is held low.
RCLK2EN:
The receive clock enable (RCLK2EN) bit controls the gating of the RCLK2 output clock.
When RCLK2EN is set to logic 1, the RCLK2 output clock operates normally. When
RCLK2EN is set to logic 0, the RCLK2 output clock is held low.
RCLK3EN:
The receive clock enable (RCLK3EN) bit controls the gating of the RCLK3 output clock.
When RCLK3EN is set to logic 1, the RCLK3 output clock operates normally. When
RCLK3EN is set to logic 0, the RCLK3 output clock is held low.
Proprietary and Confidentail to PMC-Sierra Inc., and for its Customer’s Internal Use
130
PMC [ PMC-SIERRA, INC ]
