PMC-Sierra, Inc.
PRELIMINARY
PM5381 S/UNI-2488
DATASHEET
PMC-2000489
ISSUE 1
SATURN USER NETWORK INTERFACE FOR 2488 MBIT/S
Register 0031H: SRLI PGM Clock Configuration
Bit
Type
Function
Default
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Unused
Unused
Unused
Unused
Unused
Unused
Unused
Bit 8
Unused
Bit 7
Unused
Bit 6
Unused
Bit 5
Unused
Bit 4
Unused
Bit 3
R/W
R/W
R/W
R/W
PGMRCLKSRC[1]
PGMRCLKSRC[0]
PGMRCLKSEL
PGMRCLKEN
0
0
0
0
Bit 2
Bit 1
Bit 0
The PGM Clock Configuration Register is provided at SRLI r/w address 0031H.
PGMRCLKEN:
The programmable receive clock enable (PGMRCLKEN) bit controls the gating of the
PGMRCLK output clock. When PGMRCLKEN is set to logic one, the PGMRCLK output
clock operates normally. When PGMRCLKEN is set to logic zero, the PGMRCLK output
clock is held low.
PGMRCLKSEL
The programmable receive clock frequency selection (PGMRCLKSEL) bit selects the
frequency of the PGMRCLK output clock. When PGMRCLKSEL is set high, PGMRCLK is a
nominal 8 KHz clock. When PGMRCLKSEL is set to logic zero, PGMRCLK is a nominal
19.44 MHz clock.
Proprietary and Confidentail to PMC-Sierra Inc., and for its Customer’s Internal Use
132
PMC [ PMC-SIERRA, INC ]
