欢迎访问ic37.com |
会员登录 免费注册
发布采购

PM5381 参数 Datasheet PDF下载

PM5381图片预览
型号: PM5381
PDF下载: 下载PDF文件 查看货源
内容描述: SATURN用户网络接口,用于2488 Mbit / s的 [SATURN USER NETWORK INTERFACE FOR 2488 MBIT/S]
分类和应用: 网络接口
文件页数/大小: 487 页 / 2424 K
品牌: PMC [ PMC-SIERRA, INC ]
 浏览型号PM5381的Datasheet PDF文件第142页浏览型号PM5381的Datasheet PDF文件第143页浏览型号PM5381的Datasheet PDF文件第144页浏览型号PM5381的Datasheet PDF文件第145页浏览型号PM5381的Datasheet PDF文件第147页浏览型号PM5381的Datasheet PDF文件第148页浏览型号PM5381的Datasheet PDF文件第149页浏览型号PM5381的Datasheet PDF文件第150页  
PMC-Sierra, Inc.  
PRELIMINARY  
PM5381 S/UNI-2488  
DATASHEET  
PMC-2000489  
ISSUE 1  
SATURN USER NETWORK INTERFACE FOR 2488 MBIT/S  
Register 0012H: Rx2488 Analog CRU Clock Training Configuration and Status  
Bit  
Type  
R/W  
R/W  
R/W  
R/W  
R/W  
R/W  
R/W  
R/W  
R/W  
R/W  
R/W  
R
Function  
LOS_COUNT[4]  
LOS_COUNT[3]  
LOS_COUNT[2]  
LOS_COUNT[1]  
LOS_COUNT[0]  
FILL_LEVEL[5]  
FILL_LEVEL[4]  
FILL_LEVEL[3]  
FILL_LEVEL[2]  
FILL_LEVEL[1]  
FILL_LEVEL[0]  
TRAIN  
Default  
Bit 15  
Bit 14  
Bit 13  
Bit 12  
Bit 11  
Bit 10  
Bit 9  
Bit 8  
Bit 7  
Bit 6  
Bit 5  
Bit 4  
Bit 3  
Bit 2  
Bit 1  
Bit 0  
1
0
0
0
0
1
1
0
0
0
0
0
0
0
1
1
R/W  
R/W  
R/W  
R/W  
OUTLOCK  
OUTDATA  
INLOCK  
INDATA  
The CRU Clock Training Configuration register is provided at RCS_2488 read/write address 2.  
INDATA:  
The clock difference detector DATA TO LOCK transition configuration bit determines the  
number of times the clock difference detector must pass before the CRU control state  
machine transitions from the LOCKED TO REFERENCE state to the DATA IN RANGE state.  
When INDATA is a logic zero, the clock difference detector must pass once before the state  
transition can occur. When INDATA is a logic one, the clock difference detector must pass 39  
consecutive times before the state transition can occur.  
INLOCK:  
The clock difference detector LOCKING TO DATA transition configuration bit determines the  
number of times the clock difference detector must pass before the CRU control state  
machine transitions from the DATA IN RANGE state to the LOCKED TO DATA state. When  
INLOCK is a logic zero, the clock difference detector must pass once before the state  
transition can occur. When INLOCK is a logic one, the clock difference detector must pass  
39 consecutive times before the state transition can occur.  
OUTDATA:  
The clock difference detector DROPPING OUT OF LOCK transition configuration bit  
determines the number of times the clock difference detector must fail before the CRU control  
state machine transitions from the DATA IN RANGE state to the LOCKED TO REFERENCE  
state. When OUTDATA is a logic zero, the clock difference detector must fail once before the  
Proprietary and Confidentail to PMC-Sierra Inc., and for its Customer’s Internal Use  
125