PMC-Sierra, Inc.
PRELIMINARY
PM5381 S/UNI-2488
DATASHEET
PMC-2000489
ISSUE 1
SATURN USER NETWORK INTERFACE FOR 2488 MBIT/S
Table 8 CRU Mode Control
MODE BITS
Description
7
Override Lock to Data. When high forces the
CRU to remain locked to the reference clock.
When low the CRU state machine controls the
CRU.
6:5
Loop Filter Modes:
00 = 1.25 K ohm
01 = 2.5 K ohm
10 = 5.0 K ohm
11 = 10 K ohm
The default is 2.5 K ohm
Disable Narrow-banding feature (i.e. current
offset). Active High
Enable CSU Narrow-banding and disable on-
board ICO current offset. Active High
Override Lock to Reference. When high forces
the CRU to remain locked to the data. When low
the CRU state machine controls the CRU.
Rate Select Bits:
4
3
2
1:0
00 = OC3
01 = OC48
10 = OC12
11 = OC48
CSU_CLOCK:
The Clock Source Unit Reference Clock selection bit is used to select the source of the CSU
clock. If CSU_CLOCK is set to logic 1 the clock for CSUCLKI input Pin is used as the
reference. If CSU_CLOCK is set to logic 0 than the reference clock is obtained from the CRU.
IDDQ_ENABLE:
The IDDQ_ENABLE bit activates the IDDQ (Quiescent Current) test mode. When set to ‘1’
all Analog Circuits are disabled and the IDDQ of the digital circuits can be measured. When
this bit is set to ‘0’ all analog circuits operate normally. This bit is only used during production
testing.
CRU_ENABLE:
The Clock Recovery Unit Enable provides a global power down of the CRU Analog Block
Circuit. When set to ‘0’ this bit forces the ABC to a low power state and functionality is
disabled. When set to ‘1’ the ABC operates in the normal mode of operation.
Proprietary and Confidentail to PMC-Sierra Inc., and for its Customer’s Internal Use
123
PMC [ PMC-SIERRA, INC ]
