S/UNI®-8x155 ASSP Telecom Standard Product Data Sheet
Released
Register 0x1000: S/UNI-8x155 Clock Source Configuration
Bit
Type
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Function
Unused
RSEL[2]
RSEL[1]
RSEL[0]
Unused
TSEL[2]
TSEL[1]
TSEL[0]
Default
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
0
0
0
0
0
0
This register configures the clock sources for the RCLK and TCLK interfaces.
TSEL[2:0]:
The TSEL[2:0] bits are used to select the channel that drives the TCLK and TFPO output
pins of the S/UNI-8x155. The value specified by TSEL[2:0] is the channel that controls the
TCLK and TFPO outputs.
Since the TFPI input is sampled by the rising edge of TCLK, the TFPI input is affected by
TSEL[2:0] configuration. A channel may use TFPI input (TFPEN register in the channel’s
Master Configuration #1 register is set high) only if the channel’s TCLK is frequency
locked to the TCLK of the channel selected by TSEL[2:0]. In general, channel’s operating
in loop timed must set TFPEN low.
RSEL[2:0]
The RSEL[2:0] bits are used to select the channel that drives the RCLK and RFPO output
pins of the S/UNI-8x155. The value specified by RSEL[2:0] is the channel that controls the
RCLK and RFPO outputs.
Proprietary and Confidential to PMC-Sierra, Inc., and for its customers’ internal use.
Document No.: PMC- 2010299, Issue 2
303
PMC [ PMC-SIERRA, INC ]
