S/UNI®-8x155 ASSP Telecom Standard Product Data Sheet
Released
Register 0x1004: APS Configuration and Status
Bit
Type
Function
Unused
Unused
Unused
FERRE
Unused
Reserved
TAPS55
APSTIP
Default
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
X
X
X
0
X
0
0
0
R/W
R/W
R/W
R
This register controls the APS serial interfaces. Specifically, the RAOP, TAOP and RAPS
blocks used for APS functionality.
APSTIP:
The APSTIP bit is set to a logic one when the APS performance monitor registers are being
loaded. Writing to the APS Interrupt Status register (0x1006) initiates an accumulation
interval transfer and loads all the performance monitor registers in the RAOP blocks.
Writing to the S/UNI-8x155 Master Reset and Identity register (0x000) will also cause the
APS performance monitor registers to be loaded.
APSTIP remains high while the transfer is in progress, and is set to a logic zero when the
transfer is complete. APSTIPO can be polled by a microprocessor to determine when the
accumulation interval transfer is complete.
TAPS55:
The force transmit APS (TAPS55) forces the transmit APS serial interfaces to transmit a
constant 1/0 pattern. When TAPS55 is set high, the transmit APS serial interfaces are
forced to a constant alternating value. When TAPS55 is set low, the transmit APS serial
interfaces operated normally.
This feature is used for analog testing of the APS interfaces only.
FERRE:
The FIFO error interrupt enable controls the assertion of the INTB output when one of the
FERRI[1:0] bits are high. When FERRE is set high, an interrupt is generated upon
assertion of one or more of the FERRI[1:0] registers. When FERRE is set low, changes in
the FERRI[1:0] status do not generate an interrupt.
Proprietary and Confidential to PMC-Sierra, Inc., and for its customers’ internal use.
Document No.: PMC- 2010299, Issue 2
305
PMC [ PMC-SIERRA, INC ]
