S/UNI®-8x155 ASSP Telecom Standard Product Data Sheet
Released
Register 0x0E2, 0x1E2, 0x2E2, 0x3E2, 0x4E2, 0x5E2, 0x6E2, 0x7E2:
RASE Configuration/Control
Bit
Type
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Function
Z1/S1_CAP
SFBERTEN
SFSMODE
SFCMODE
SDBERTEN
SDSMODE
SDCMODE
Reserved
Default
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
0
0
0
0
0
0
0
0
SDCMODE:
The SDCMODE alarm bit selects the RASE window size to use for clearing the SD alarm.
When SDCMODE is a logic zero the RASE clears the SD alarm using the same window
size used for declaration. When SDCMODE is a logic one the RASE clears the SD alarm
using a window size that is 8 times longer than the alarm declaration window size. The
declaration window size is determined by the RASE SD Accumulation Period registers.
SDSMODE:
The SDSMODE bit selects the RASE saturation mode. When SDSMODE is a logic zero
the RASE limits the number of B2 errors accumulated in one frame period to the RASE SD
Saturation Threshold register value. When SDSMODE is a logic one the RASE limits the
number of B2 errors accumulated in one window subtotal accumulation period to the RASE
SD Saturation Threshold register value. Note that the number of frames in a window
subtotal accumulation period is determined by the RASE SD Accumulation Period register
value.
SDBERTEN:
The SDBERTEN bit selects automatic monitoring of line bit error rate threshold events by
the RASE. When SDBERTEN is a logic one, the RASE continuously monitors line BIP
errors over a period defined in the RASE configuration registers. When SDBERTEN is a
logic zero, the RASE BIP accumulation logic is disabled, and the RASE logic is reset to the
declaration monitoring state.
All RASE accumulation period and threshold registers should be set up before SDBERTEN
is written.
Proprietary and Confidential to PMC-Sierra, Inc., and for its customers’ internal use.
Document No.: PMC- 2010299, Issue 2
284
PMC [ PMC-SIERRA, INC ]
