S/UNI®-8x155 ASSP Telecom Standard Product Data Sheet
Released
Register 0x0E1, 0x1E1, 0x2E1, 0x3E1, 0x4E1, 0x5E1, 0x6E1, 0x7E1:
RASE Interrupt Status
Bit
Type
R
R
R
R
R
R
R
R
Function
PSBFI
COAPSI
Z1/S1I
SFBERI
SDBERI
SFBERV
SDBERV
PSBFV
Default
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
X
X
X
X
X
X
X
X
PSBFV:
The PSBFV bit indicates the protection switching byte failure alarm state. The alarm is
declared (PSBFV is set high) when twelve successive frames have been received without
three consecutive frames containing identical K1 bytes. The alarm is removed (PSBFV is
set low) when three consecutive frames containing identical K1 bytes have been received.
SDBERV:
The SDBERV bit indicates the signal degrade threshold crossing alarm state. The alarm is
declared (SDBERV is set high) when the bit error rate exceeds the threshold programmed in
the RASE SD Declaring Threshold registers. The alarm is removed (SDBERV is set low)
when the bit error rate is below the threshold programmed in the RASE SD Clearing
Threshold registers.
SFBERV:
The SFBERV bit indicates the signal failure threshold crossing alarm state. The alarm is
declared (SFBERV is set high) when the bit error rate exceeds the threshold programmed in
the RASE SF Declaring Threshold registers. The alarm is removed (SFBERV is set low)
when the bit error rate is below the threshold programmed in the RASE SF Clearing
Threshold registers.
SDBERI:
The SDBERI bit is set high when the signal degrade threshold crossing alarm is declared or
removed. This bit is cleared when the RASE Interrupt Status register is read.
SFBERI:
The SFBERI bit is set high when the signal failure threshold crossing alarm is declared or
removed. This bit is cleared when the RASE Interrupt Status register is read.
Proprietary and Confidential to PMC-Sierra, Inc., and for its customers’ internal use.
Document No.: PMC- 2010299, Issue 2
282
PMC [ PMC-SIERRA, INC ]
