S/UNI®-8x155 ASSP Telecom Standard Product Data Sheet
Released
Z1/S1I:
The Z1/S1I bit is set high when a new synchronization status message has been extracted
into the RASE Receive Z1/S1 register. This bit is cleared when the RASE Interrupt Status
register is read.
COAPSI:
The COAPSI bit is set high when a new APS code value has been extracted into the RASE
Receive K1 and RASE Receive K2 registers. This bit is cleared when the RASE Interrupt
Status register is read.
PSBFI:
The PSBFI bit is set high when the protection switching byte failure alarm is declared or
removed. This bit is cleared when the RASE Interrupt Status register is read.
Proprietary and Confidential to PMC-Sierra, Inc., and for its customers’ internal use.
Document No.: PMC- 2010299, Issue 2
283
PMC [ PMC-SIERRA, INC ]
