S/UNI®-8x155 ASSP Telecom Standard Product Data Sheet
Released
Register 0x0E5, 0x1E5, 0x2E5, 0x3E5, 0x4E5, 0x5E5, 0x6E5, 0x7E5:
RASE SF Accumulation Period MSB
Bit
Type
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Function
SFSAP[23]
SFSAP[22]
SFSAP[21]
SFSAP[20]
SFSAP[19]
SFSAP[18]
SFSAP[17]
SFSAP[16]
Default
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
0
0
0
0
0
0
0
0
SFSAP[23:0]:
The SFSAP[23:0] bits represent the number of 8 KHz frames used to accumulate the B2
error subtotal. The total evaluation window to declare the SF alarm is broken into 8
subtotals, so this register value represents 1/8 of the total sliding window size. Refer to the
Operations section for recommended settings.
Proprietary and Confidential to PMC-Sierra, Inc., and for its customers’ internal use.
Document No.: PMC- 2010299, Issue 2
287
PMC [ PMC-SIERRA, INC ]
