S/UNI®-8x155 ASSP Telecom Standard Product Data Sheet
Released
Register 0x080, 0x180, 0x280, 0x380, 0x480, 0x580, 0x680, 0x780:
TXCP Configuration 1
Bit
Type
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Function
Reserved
Reserved
HSCR
Reserved
HCSB
HCSADD
DSCR
FIFORST
Default
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
0
0
0
0
0
1
0
0
FIFORST:
The FIFORST bit is used to reset the channel four cell transmit buffer. When FIFORST is
set to logic zero, the buffer operates normally. When FIFORST is set to logic one, the
buffer is immediately emptied and ignores writes. The buffer remains empty and continues
to ignore writes until a logic zero is written to FIFORST. Null/unassigned cells are
transmitted until a subsequent cell is written to the buffer.
The FIFORST must be set high before the per-channel reset in the TUL3 is asserted. The
FIFORST must be set low after the per-channel reset in the TUL3 is deasserted.
DSCR:
The DSCR bit controls the scrambling of the cell payload. When DSCR is a logic one, cell
payload scrambling is disabled. When DSCR is a logic zero, payload scrambling is
enabled.
HCSADD:
6
4
2
The HCSADD bit controls the addition of the coset polynomial, x +x +x +1, to the HCS
octet prior to insertion in the synchronous payload envelope. When HCSADD is a logic
one, the polynomial is added, and the resulting HCS is inserted. When HCSADD is a logic
zero, the polynomial is not added, and the unmodified HCS is inserted. HCSADD takes
effect unconditionally regardless of whether a null/unassigned cell is being transmitted or
whether the HCS octet has been read from the FIFO.
HCSB:
The active low HCSB bit enables the internal generation and insertion of the HCS octet into
the transmit cell stream. When HCSB is logic zero, the HCS is generated and inserted
internally. If HCSB is logic one , then no HCS octet is inserted in the transmit data stream.
Proprietary and Confidential to PMC-Sierra, Inc., and for its customers’ internal use.
Document No.: PMC- 2010299, Issue 2
234
PMC [ PMC-SIERRA, INC ]
