S/UNI®-8x155 ASSP Telecom Standard Product Data Sheet
Released
Register 0x06D, 0x16D, 0x26D, 0x36D, 0x46D, 0x56D, 0x66D, 0x76D:
RXCP Receive Cell Counter MSB
Bit
Type
R
R
R
R
R
R
R
R
Function
RCELL[23]
RCELL[22]
RCELL[21]
RCELL[20]
RCELL[19]
RCELL[18]
RCELL[17]
RCELL[16]
Default
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
X
X
X
X
X
X
X
X
RCELL[23:0]:
The RCELL[23:0] bits indicate the number of cells received and written into the receive
FIFO during the last accumulation interval. Cells received and filtered due to HCS errors or
Idle cell matches are not counted. The counter should be polled every second to avoid
saturation. The contents of these registers are valid a maximum of 67 RCLK periods after a
transfer is triggered by a write to one of RXCP's performance monitor counters.
The count can also be polled by writing to the S/UNI-8x155 Master Reset and Identity
register (0x000). Writing to register address 0x000 loads all counter registers in all
channels and APS links.
The count can also be polled by writing to the channel Master Interrupt Status register
(offset 0x07). Writing to register offset 0x07 loads all counter registers in the RSOP, RLOP,
RPOP, SPTB, SSTB, RXCP, TXCP, RXFP, and TXFP blocks of the channel.
Proprietary and Confidential to PMC-Sierra, Inc., and for its customers’ internal use.
Document No.: PMC- 2010299, Issue 2
231
PMC [ PMC-SIERRA, INC ]
