S/UNI®-8x155 ASSP Telecom Standard Product Data Sheet
Released
Register 0x082, 0x182, 0x282, 0x382, 0x482, 0x582, 0x682, 0x782:
TXCP Cell Count Status
Bit
Type
R/W
R
Function
XFERE
XFERI
Default
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
0
X
X
X
1
0
0
0
R
OVR
Unused
Reserved
Reserved
Reserved
Reserved
R/W
R/W
R/W
R/W
XFERI:
The XFERI bit indicates that a transfer of Transmit Cell Count data has occurred. A logic
one in this bit position indicates that the Transmit Cell Count registers have been updated.
This update is initiated by writing to one of the Transmit Cell Count register locations, to
the S/UNI-8x155 Master Reset and Identity register or to the channel Master Interrupt
Status register. XFERI is set low when this register is read.
OVR:
The OVR bit is the overrun status of the Transmit Cell Count registers. A logic one in this
bit position indicates that a previous transfer (indicated by XFERI being logic one) has not
been acknowledged before the next accumulation interval has occurred and that the contents
of the Transmit Cell Count registers have been overwritten. OVR is set low when this
register is read.
XFERE:
The XFERE bit enables the generation of an interrupt when an accumulation interval is
completed and new values are stored in the Transmit Cell Count registers. When XFERE is
set high, the interrupt is enabled.
Reserved:
These bits should be set to their default values for proper operation.
Proprietary and Confidential to PMC-Sierra, Inc., and for its customers’ internal use.
Document No.: PMC- 2010299, Issue 2
237
PMC [ PMC-SIERRA, INC ]
