S/UNI®-8x155 ASSP Telecom Standard Product Data Sheet
Released
Register 0x083, 0x183, 0x283, 0x383, 0x483, 0x583, 0x683, 0x783:
TXCP Interrupt Enable/Status
Bit
Type
R/W
R/W
R/W
Function
Reserved
FOVRE
Reserved
Unused
Unused
Reserved
FOVRI
Default
0
0
0
X
X
X
X
X
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
R
R
R
Reserved
FOVRI:
The FOVRI bit is set high when an attempt is made to write into the FIFO when it is already
full. This bit is reset immediately after a read to this register.
FOVRE:
The FOVRE bit enables the generation of an interrupt due to an attempt to write the FIFO
when it is already full. When FOVRE is set to logic one, the interrupt is enabled.
Reserved:
All reserved bits must be programmed to zero for proper operation.
Proprietary and Confidential to PMC-Sierra, Inc., and for its customers’ internal use.
Document No.: PMC- 2010299, Issue 2
238
PMC [ PMC-SIERRA, INC ]
