S/UNI®-8x155 ASSP Telecom Standard Product Data Sheet
Released
Register 0x070, 0x170, 0x270, 0x370, 0x470, 0x570, 0x670, 0x770:
RXCP Idle Cell Counter MSB
Bit
Type
R
R
R
R
R
R
R
R
Function
ICELL[23]
ICELL[22]
ICELL[21]
ICELL[20]
ICELL[19]
ICELL[18]
ICELL[17]
ICELL[16]
Default
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
X
X
X
X
X
X
X
X
ICELL[23:0]:
The ICELL[23:0] bits indicate the number of idle cells received during the last
accumulation interval. The counter should be polled every second to avoid saturation. The
contents of these registers are valid a maximum of 67 RCLK periods after a transfer is
triggered by a write to one of RXCP's performance monitor counters.
The count can also be polled by writing to the S/UNI-8x155 Master Reset and Identity
register (0x000). Writing to register address 0x000 loads all counter registers in all
channels and APS links.
The count can also be polled by writing to the channel Master Interrupt Status register
(offset 0x07). Writing to register offset 0x07 loads all counter registers in the RSOP, RLOP,
RPOP, SPTB, SSTB, RXCP, TXCP, RXFP, and TXFP blocks of the channel.
Proprietary and Confidential to PMC-Sierra, Inc., and for its customers’ internal use.
Document No.: PMC- 2010299, Issue 2
233
PMC [ PMC-SIERRA, INC ]
